The present invention relates to a semiconductor device of a chip size package type (hereinafter called as “CSP type”), and more particularly to a semiconductor device in which external connection terminal portions project from a bottom surface side of an encapsulating resin as well as a method of manufacturing the same.
Tape CSP type semiconductor devices using polyimide resin tape and solder balls and bump chip carrier type (hereinafter called as “BCC type”) semiconductor devices using a base metal are known, reflecting demands for the miniaturization of semiconductor devices. However, the tape CSP type semiconductor devices have problems in that the polyimide resin tape is expensive, and that the polyimide resin tape is not suitable for strip transport since it is soft. Meanwhile, the BCC type semiconductor devices have a problem in that after the base metal is removed by etching, discrete devices are left, so that their molded surfaces need to be fixed by pressure sensitive adhesive tape, resulting in high cost. Accordingly, the present assignee earlier proposed a method of manufacturing a semiconductor device disclosed in patent document 1.
An example of this method of manufacturing a semi-conductor device is shown generally in FIGS. 7A to 7J. However, as explained below, certain of the steps shown in FIGS. 7A-7J were not practiced in the noted prior art. As further explained below, certain component compositions were not used in the prior art. After a resist film 11 is coated on the overall obverse and reverse surfaces of a leadframe material 10 constituted of Cu, a Cu alloy, or an iron-nickel alloy (e.g., 42 alloy), the resist film 11 is exposed with a predetermined lead pattern, and development is then carried out, thereby forming an etching pattern 12 of the plating mask. Then, the leadframe material 10 is subjected to all-over plating, and if the resist film 11 is removed, plating masks 13 and 14 are formed on the obverse and reverse sides (steps A to D).
Next, after the entire lower surface (i.e., the reverse surface side) is coated with another resist film 15, in a manner not performed in the noted prior art, the upper surface side (i.e., the obverse surface side) is subjected to half etching by using the plating mask 13 as a resist mask. In this case, since that portion of the surface of the leadframe material 10 which is covered by the plating mask 13 is not etched, an element mounting portion 16 and wire bonding portions 17 formed in advance by the resist film ultimately project. It should be noted that the surfaces of the element mounting portion 16 and the wire bonding portions 17 are covered by the plating mask 13 (steps E and F).
Next, after removing the resist film 15 on the lower surface side, a semiconductor element 18 is mounted on the element mounting portion 16, and electrode pad portions of the semiconductor element 18 and the wire bonding portions 17 are wire bonded, the semiconductor element 18, bonding wires 20, and the wire bonding portions 17 are resin encapsulated. Reference numeral 21 denotes an encapsulating resin (steps F and H).
Subsequently, the reverse surface side is subjected to half etching. At this time, the portion of the leadframe material 10 where the plating mask 14 is formed remains without being etched since the plating mask 14 acts as a resist mask. As a result, reverse surfaces of external connection terminal portions 22 and the element mounting portion 16 project. Since the external connection terminal portions 22 and the wire bonding portions 17 communicate with each other, the respective external connection terminal portions 22 (and the wire bonding portions 17 communicating therewith) are made independent and are electrically connected to the respective electrode pad portions of the semiconductor element 18. Since these semiconductor devices 23 are generally arranged in grid form and are manufactured simultaneously, they are diced and separated (discretized), thereby manufacturing individual semiconductor devices 23 (steps I and J).
[Patent Document 1] JP-A-2001-24135
However, with the above-described semiconductor devices, the corresponding plating masks 13′ and 14′ are conventionally formed, as shown in FIG. 8. Namely, the plating masks 13′ and 14′ are formed by providing, for instance, an Ni undercoat 24′ with a thickness of 1 μm on the surfaces (including the reverse surface) of the leadframe material 10′, and by further providing thereon noble metal plating (e.g., Au) 25′ with a thickness of approx. 0.2 μm. Since the noble metal plating 25′ on the upper layer side (a layer farther from the leadframe material 10′ is referred to as the upper layer, and a layer close thereto is referred to as the lower layer) has etching solution resistance, the noble metal plating 25′ is not eroded during etching, but the leadframe material 10′ formed of copper or a copper alloy and the Ni undercoat 24′ on the lower layer side are eroded by an etching solution, as shown in FIG. 9A. Hence, the periphery of the noble metal plating 25′ assumes a foil-like shape, and is adhered to the periphery of each of the wire bonding portions 17′, the element mounting portion 16′, and the external connection terminal portions 22′, thereby forming plating burrs (plating foils) 26′.
If such plating burrs 26′ are present, the plating burrs 26′ are exfoliated in the wire bonding process, the resin encapsulating process (i.e., molding process), and the like, causing defects in semiconductor devices including faulty wire bonding, and short-circuiting between terminals, and the like.